EMBEDDED COMPUTING SYSTEM DESIGN (MEVD-205)

Rajiv Gandhi Technological University, Bhopal (MP)

M.E./ M.Tech. Embedded System and VLSI Design SVITS(INDR)

SEMESTER-II  MEVD – 205 EMBEDDED COMPUTING DESIGN

UNIT I
Introduction:Embedding Complex Systems and Microprocessors, Embedded System Design Process, Designing Hardware and Software Components,Formalization of System Design, Application Examples.
 

UNIT II
Instruction Sets:Assembly Language, ARM processor and memory organization.Data Operations and Control of Flow. SHARC Processor, Memory organization,Data Operations and flow control, Parallelism within the instructions.
 

UNIT III
CPUs:Performance, Power Dissipation, Design Example, Data Compression.CPU Bus Protocols in ARM, Design, Development and Debugging.
 

UNIT IV
Program design and Analysis:Program Design, Models of Program, Assembling,Linking, Compiling, Analysis and optimization of the Program Size and Execution times. Design Example: Software Modem.

UNIT V

System Design Techniques:Design Methodologies, Requirement Analysis,Specifications, System Analysis, quality Assurance, Two Design Examples in Networking and Internet Enabled Systems and Automobile Applications.

TEXT / REFERENCE BOOKS:

• Wayne Wolf, Computers as Components, Harcourt India Private Ltd.

MICRO ELECTRONICS (MEVD-204)

Rajiv Gandhi Technological University, Bhopal (MP)

M.E./ M.Tech. Embedded System and VLSI Design SVITS(INDR)

SEMESTER-II  MEVD – 204 MICRO ELECTRONICS

UNIT-I
Review of quantum mechanics theory:Motion of electron in a periodic lattice. Band theory of solids, effective mass, holes.

UNIT-II
Statistics of carriers in semiconductors:Lifetime and recombination theory.Boltzmann transports equation. Carrier transport in semiconductors, including high field effect.

UNIT- III

P-N junction theory:Excess currents and breakdown in p-n junctions. Bipolar transistors. Ebers-Moll and small signal models. Switching characteristics. Nonuniformly doped transistors. High current and high frequency effects.

TEXT / REFERENCE BOOKS

• J.L. Moll, Physics of Semiconductors, McGraw Hill

• F.Y. Wang, Introduction to Solid State Electronics, North Holland.

• S.M. Sze, Physics of Semiconductor Devices, Weiley Easter.

• D.J. Roulston, Dipolar Semiconductors Devices, McGraw Hill

• R.L. Pritchnard, Electrical Characteristics of Transistors, McGraw Hill

VLSI TEST AND TESTABILITY (MEVD-203)

Rajiv Gandhi Technological University, Bhopal (MP)

M.E./ M.Tech. Embeded System and VLSI Design SVITS(INDR)

(ELECTIVE-I)  VLSI TEST AND TESTABILITY

UNIT- I

Introduction to Testing Process:CMOS Testing, Reliability, Failures & Faults, Levels of Testing, Test economics, Elementary Testing Concepts, System and Field Testing, Burn in boards.

UNIT- II

Logic Simulation & Fault modelling: Delay Models, Event driven simulation, general fault simulation, fault detection and redundancy, fault equivalence and fault dominance. Stuck-at faults, bridging faults, transistor faults, delay faults etc. Fault detection using Boolean Difference, Path Sensitization. Fault Collapsing

UNIT- III

Test generation for combinational & sequential circuits:D-algorithm, PODEM, SPOOF. Automatic Test Pattern Generation. Primitive and Propagation Cubes. Fanout Oriented Test Generation. Controllability and Observability. Testing of sequential circuits as iterative combinational circuits, state table verification, random testing.

UNIT- IV
Design for testability: Ad-hoc methods, Full scan & Partial scan design. Boundary scans. Testability analysis.

UNIT- V

Built-in self-test & IDDQ testing: RAM BIST, Logic BIST Random and weighted random pattern testability BIST Pattern generator and response analyzer Scan-based BIST architecture Test point insertion for improving random testability. IDDQ testing, IDDQ test patterns, IDDQ measurement Case studies, Design for IDDQ testability

TEXT / REFERENCE BOOKS:

• N. Weste and K. Eshraghian, Principles of CMOS VLSI design, Addison-Wesley.

• Parag K. Lala, Fault Tolerant and Fault Testable Hardware Design, BS Publication.

REAL TIME OPERATING SYSTEM (MEVD-202)

Rajiv Gandhi Technological University, Bhopal (MP)

M.E./ M.Tech. Embeded System and VLSI Design SVITS(INDR)

REAL TIME OPERATING SYSTEM (MEVD-202)

 UNIT-I

Introduction to OS: Process Management & Inter Process Communication. Memory management, I/O subsystem, File System Organization.

UNIT II

Real Time Systems Concepts: Foreground/Background Systems, Critical Section of Code, Resource, Shared resource, Multitasking, task, context switch, Kernel, Schedules, Premptive & Non-Premptive Kernel, various scheduling methods.

Real Time Scheduling. Real-Time task scheduling: Clock-driven, Event-driven, Scheduling of real-time task on a uniprocessor. Rate Monotonic Analysis (RMA), Earliest Deadline First (EDF), Scheduling with limited priority levels

UNIT-III

Kernel structure:Task scheduling, Task management, Resource sharing among tasks,Priority inversion problem, Priority inheritance protocol An overview of scheduling in multiprocessor and distributed systems

UNIT-IV

Performance Metrics of RTOS: Programming in VxWorks, or μCOS-II Overview of μC/OS-II Overview of some other commercial embedded operating systems: PSOS, VRTX, RT Linux, Win CE.Benchmarking real-time operating systems.

UNIT-V

Commercial real-time operating systems: Unix as a real-time operating system, Windows as a real-time operating system, Extensions to Unix : Host target approach, Preemption points, Fully preemptable kernel

TEXT / REFERENCE BOOKS:

• Jean J. Labrosse, MicroC/OS-II, The Real Time Kernel

• VxWorks details from Internet.

• μC/OS-II Manuals

• David E. Simon, An Embedded Software Primer, Pearson Education

• Dr. Rajib Mall, Real time Systems, Theory and practices, Pearson Education.

VLSI TECHNOLOGY (MEVD-201)

Rajiv Gandhi Technological University, Bhopal (MP)

M.E./ M.Tech. Embeded System and VLSI Design SVITS(INDR)

MEVD – 201 VLSI TECHNOLOGY

UNIT  I

Overview of Semiconductor Processing:Electronic grade silicon preparation,Crystal growth,Czochralski process,wafer-preparation ,slicing,Marking, polishing,evaluation. Basic wafer fabrication operations,wafer sort,clean room construction and maintenance.

UNIT II

Oxidation:Objectives,Silicon dioxide layer uses,Thermal oxidation mechanism and methods, Kinetics of oxidation,Deal Grove model,Oxidation processes,post oxidation evaluation.

UNIT III

Basic Patterning: Overview of Photo-masking process, Ten step process, Basic photoresist chemistry, comparison of positive and negative photoresists, X-ray lithography, Electron beam exposure system.

UNIT IV

Doping:Definition of a junction, Formation of doped region and junction by diffusion, diffusion process steps,deposition,drive-in-oxidation,Ion implantation -concept and system, implant damage,Comparison of diffusion and ion-implantation techniques.

UNIT V

Deposition:Chemical Vapor Deposition (CVD), CVD Process steps,CVD System types, Low- Pressure CVD (LPCVD),Plasma-enhanced CVD (PECVD),Vapor Phase Epitaxy (VPE), Molecular Beam Epitaxy (MBE), Metalorganic CVD (MOCVD),SOS (Silicon on Sapphire) and SOI (silicon on Insulator).Brief Introduction to Metallization.

TEXT / REFERENCE BOOKS:

• S.M. Sze, VLSI Technology, McGraw-Hill, 2nd Ed.

• S. K. Gandhi, VLSI Fabrication Principles, Wiley

VLSI DESIGN II - SEM SYLLABUS

• VLSI TECHNOLOGY (MEVD-201) 

• REAL TIME OPERATING SYSTEM (MEVD-202) 

• VLSI TEST AND TESTABILITY (MEVD-203)  

• MICRO ELECTRONICS (MEVD-204) 

• EMBEDDED COMPUTING SYSTEM DESIGN (MEVD-205)