VLSI TEST AND TESTABILITY (MEVD-203)

Rajiv Gandhi Technological University, Bhopal (MP)

M.E./ M.Tech. Embeded System and VLSI Design SVITS(INDR)

(ELECTIVE-I)  VLSI TEST AND TESTABILITY

UNIT- I

Introduction to Testing Process:CMOS Testing, Reliability, Failures & Faults, Levels of Testing, Test economics, Elementary Testing Concepts, System and Field Testing, Burn in boards.

UNIT- II

Logic Simulation & Fault modelling: Delay Models, Event driven simulation, general fault simulation, fault detection and redundancy, fault equivalence and fault dominance. Stuck-at faults, bridging faults, transistor faults, delay faults etc. Fault detection using Boolean Difference, Path Sensitization. Fault Collapsing

UNIT- III

Test generation for combinational & sequential circuits:D-algorithm, PODEM, SPOOF. Automatic Test Pattern Generation. Primitive and Propagation Cubes. Fanout Oriented Test Generation. Controllability and Observability. Testing of sequential circuits as iterative combinational circuits, state table verification, random testing.

UNIT- IV
Design for testability: Ad-hoc methods, Full scan & Partial scan design. Boundary scans. Testability analysis.

UNIT- V

Built-in self-test & IDDQ testing: RAM BIST, Logic BIST Random and weighted random pattern testability BIST Pattern generator and response analyzer Scan-based BIST architecture Test point insertion for improving random testability. IDDQ testing, IDDQ test patterns, IDDQ measurement Case studies, Design for IDDQ testability

TEXT / REFERENCE BOOKS:

• N. Weste and K. Eshraghian, Principles of CMOS VLSI design, Addison-Wesley.

• Parag K. Lala, Fault Tolerant and Fault Testable Hardware Design, BS Publication.