EMBEDDED COMPUTING SYSTEM DESIGN (MEVD-205)

Rajiv Gandhi Technological University, Bhopal (MP)

M.E./ M.Tech. Embedded System and VLSI Design SVITS(INDR)

SEMESTER-II  MEVD – 205 EMBEDDED COMPUTING DESIGN

UNIT I
Introduction:Embedding Complex Systems and Microprocessors, Embedded System Design Process, Designing Hardware and Software Components,Formalization of System Design, Application Examples.
 

UNIT II
Instruction Sets:Assembly Language, ARM processor and memory organization.Data Operations and Control of Flow. SHARC Processor, Memory organization,Data Operations and flow control, Parallelism within the instructions.
 

UNIT III
CPUs:Performance, Power Dissipation, Design Example, Data Compression.CPU Bus Protocols in ARM, Design, Development and Debugging.
 

UNIT IV
Program design and Analysis:Program Design, Models of Program, Assembling,Linking, Compiling, Analysis and optimization of the Program Size and Execution times. Design Example: Software Modem.

UNIT V

System Design Techniques:Design Methodologies, Requirement Analysis,Specifications, System Analysis, quality Assurance, Two Design Examples in Networking and Internet Enabled Systems and Automobile Applications.

TEXT / REFERENCE BOOKS:

• Wayne Wolf, Computers as Components, Harcourt India Private Ltd.

MICRO ELECTRONICS (MEVD-204)

Rajiv Gandhi Technological University, Bhopal (MP)

M.E./ M.Tech. Embedded System and VLSI Design SVITS(INDR)

SEMESTER-II  MEVD – 204 MICRO ELECTRONICS

UNIT-I
Review of quantum mechanics theory:Motion of electron in a periodic lattice. Band theory of solids, effective mass, holes.

UNIT-II
Statistics of carriers in semiconductors:Lifetime and recombination theory.Boltzmann transports equation. Carrier transport in semiconductors, including high field effect.

UNIT- III

P-N junction theory:Excess currents and breakdown in p-n junctions. Bipolar transistors. Ebers-Moll and small signal models. Switching characteristics. Nonuniformly doped transistors. High current and high frequency effects.

TEXT / REFERENCE BOOKS

• J.L. Moll, Physics of Semiconductors, McGraw Hill

• F.Y. Wang, Introduction to Solid State Electronics, North Holland.

• S.M. Sze, Physics of Semiconductor Devices, Weiley Easter.

• D.J. Roulston, Dipolar Semiconductors Devices, McGraw Hill

• R.L. Pritchnard, Electrical Characteristics of Transistors, McGraw Hill

VLSI TEST AND TESTABILITY (MEVD-203)

Rajiv Gandhi Technological University, Bhopal (MP)

M.E./ M.Tech. Embeded System and VLSI Design SVITS(INDR)

(ELECTIVE-I)  VLSI TEST AND TESTABILITY

UNIT- I

Introduction to Testing Process:CMOS Testing, Reliability, Failures & Faults, Levels of Testing, Test economics, Elementary Testing Concepts, System and Field Testing, Burn in boards.

UNIT- II

Logic Simulation & Fault modelling: Delay Models, Event driven simulation, general fault simulation, fault detection and redundancy, fault equivalence and fault dominance. Stuck-at faults, bridging faults, transistor faults, delay faults etc. Fault detection using Boolean Difference, Path Sensitization. Fault Collapsing

UNIT- III

Test generation for combinational & sequential circuits:D-algorithm, PODEM, SPOOF. Automatic Test Pattern Generation. Primitive and Propagation Cubes. Fanout Oriented Test Generation. Controllability and Observability. Testing of sequential circuits as iterative combinational circuits, state table verification, random testing.

UNIT- IV
Design for testability: Ad-hoc methods, Full scan & Partial scan design. Boundary scans. Testability analysis.

UNIT- V

Built-in self-test & IDDQ testing: RAM BIST, Logic BIST Random and weighted random pattern testability BIST Pattern generator and response analyzer Scan-based BIST architecture Test point insertion for improving random testability. IDDQ testing, IDDQ test patterns, IDDQ measurement Case studies, Design for IDDQ testability

TEXT / REFERENCE BOOKS:

• N. Weste and K. Eshraghian, Principles of CMOS VLSI design, Addison-Wesley.

• Parag K. Lala, Fault Tolerant and Fault Testable Hardware Design, BS Publication.

REAL TIME OPERATING SYSTEM (MEVD-202)

Rajiv Gandhi Technological University, Bhopal (MP)

M.E./ M.Tech. Embeded System and VLSI Design SVITS(INDR)

REAL TIME OPERATING SYSTEM (MEVD-202)

 UNIT-I

Introduction to OS: Process Management & Inter Process Communication. Memory management, I/O subsystem, File System Organization.

UNIT II

Real Time Systems Concepts: Foreground/Background Systems, Critical Section of Code, Resource, Shared resource, Multitasking, task, context switch, Kernel, Schedules, Premptive & Non-Premptive Kernel, various scheduling methods.

Real Time Scheduling. Real-Time task scheduling: Clock-driven, Event-driven, Scheduling of real-time task on a uniprocessor. Rate Monotonic Analysis (RMA), Earliest Deadline First (EDF), Scheduling with limited priority levels

UNIT-III

Kernel structure:Task scheduling, Task management, Resource sharing among tasks,Priority inversion problem, Priority inheritance protocol An overview of scheduling in multiprocessor and distributed systems

UNIT-IV

Performance Metrics of RTOS: Programming in VxWorks, or μCOS-II Overview of μC/OS-II Overview of some other commercial embedded operating systems: PSOS, VRTX, RT Linux, Win CE.Benchmarking real-time operating systems.

UNIT-V

Commercial real-time operating systems: Unix as a real-time operating system, Windows as a real-time operating system, Extensions to Unix : Host target approach, Preemption points, Fully preemptable kernel

TEXT / REFERENCE BOOKS:

• Jean J. Labrosse, MicroC/OS-II, The Real Time Kernel

• VxWorks details from Internet.

• μC/OS-II Manuals

• David E. Simon, An Embedded Software Primer, Pearson Education

• Dr. Rajib Mall, Real time Systems, Theory and practices, Pearson Education.

VLSI TECHNOLOGY (MEVD-201)

Rajiv Gandhi Technological University, Bhopal (MP)

M.E./ M.Tech. Embeded System and VLSI Design SVITS(INDR)

MEVD – 201 VLSI TECHNOLOGY

UNIT  I

Overview of Semiconductor Processing:Electronic grade silicon preparation,Crystal growth,Czochralski process,wafer-preparation ,slicing,Marking, polishing,evaluation. Basic wafer fabrication operations,wafer sort,clean room construction and maintenance.

UNIT II

Oxidation:Objectives,Silicon dioxide layer uses,Thermal oxidation mechanism and methods, Kinetics of oxidation,Deal Grove model,Oxidation processes,post oxidation evaluation.

UNIT III

Basic Patterning: Overview of Photo-masking process, Ten step process, Basic photoresist chemistry, comparison of positive and negative photoresists, X-ray lithography, Electron beam exposure system.

UNIT IV

Doping:Definition of a junction, Formation of doped region and junction by diffusion, diffusion process steps,deposition,drive-in-oxidation,Ion implantation -concept and system, implant damage,Comparison of diffusion and ion-implantation techniques.

UNIT V

Deposition:Chemical Vapor Deposition (CVD), CVD Process steps,CVD System types, Low- Pressure CVD (LPCVD),Plasma-enhanced CVD (PECVD),Vapor Phase Epitaxy (VPE), Molecular Beam Epitaxy (MBE), Metalorganic CVD (MOCVD),SOS (Silicon on Sapphire) and SOI (silicon on Insulator).Brief Introduction to Metallization.

TEXT / REFERENCE BOOKS:

• S.M. Sze, VLSI Technology, McGraw-Hill, 2nd Ed.

• S. K. Gandhi, VLSI Fabrication Principles, Wiley

VLSI DESIGN II - SEM SYLLABUS

• VLSI TECHNOLOGY (MEVD-201) 

• REAL TIME OPERATING SYSTEM (MEVD-202) 

• VLSI TEST AND TESTABILITY (MEVD-203)  

• MICRO ELECTRONICS (MEVD-204) 

• EMBEDDED COMPUTING SYSTEM DESIGN (MEVD-205)

LAB -II (MEVD-107)

RGPV ME / M.TECH VLSI DESIGN LAB -II (MEVD-107)

RGPV VLSI DESIGM M TECH 1ST SEM LAB -II IS DIGITAL DESIGN   INTERNAL ASSESMENT =25

PRACTIACL EXAM =100
 TOTAL =125

LAB -I (MEVD-106)

LAB -1 IS EMBEDDED SYSTEM DESIGN - INTERNAL ASSESSMENT =25
                                                                          PRACTICAL EXAM = 100
                                                                           TOTAL                     =125

EMBEDDED MICRO-CONTROLLER PROGRAMMING (MEVD-105)

Rajiv Gandhi Technological University, Bhopal (MP)

M.E./ M.Tech. Embeded System and VLSI Design SVITS(INDR)

EMBEDDED MICRO CONTROLLER PROGRAMMING (MEVD-105)

UNIT-I

Embedded System Overview:Embedded System definition.Processor Technology:General purpose,Single Purpose,Application Specific,super scalar,Pipe lined,Very Long Instruction Word (VLIW) Processor, Microprocessors,Micro controllers and DSP Processors.Embedded Processors in VLSI circuit.

UNIT-II

Architectural Issues:CISC,RISC,DSP and Harvard/Princeton Architectures. Memory :ROM, EPROM,EEPROM,FLASH, RAM,SRAM, DRAM, SDRAM, NVRAM,EDORAM,DDRRAM, Memory Hierarchy and Cache.
Interfacing:Interfacing using Glue Logic,Interrupt,DMA,I/O Bus structure,I/O devices,Serial Communication Protocols,Parallel Communication Protocols,Wireless Protocols.

UNIT-III

Introduction to 8-bit Micro controllers:8051,68HC11, 80196, Timers/Counters,USART. Detailed study of 8051 microcontroller, with its programming in assembly language and Interrupts,Serial Programming etc.

UNIT-IV

Interfacing of Micro controller: SPI, PWM, WDT,Input Capture ,Output Compare Modes, Interfacing LED, Switches, ADC, DAC, LCD , RTC. Idea about the C programming of Microcontroller. I2C, CAN bus architecture.

UNIT-V

Introduction to 16/32-bit microcontrollers:Introduction to ARM Architecture & Organization, Difference between ARM ,ARM9 & ARM11 TDMI,ARM programming model,ARM Instruction set.

TEXT / REFERENCE BOOKS:

• David E. Simon, An Embedded Software Primer, Pearson Education.

• Dr. RajKamal, Embedded Systems, TMH.

• Vahid & Givargis, Embedded System Design,John Wiley & Sons.

• K. J. Ayala , 8051 Microcontrollers, Penram International, Second Edition

• M. A. Mazidi & J. G. Mazidi, 8051 Microcontroller and Embedded System, Pearson Education Asia

• J. W. Valvano, Embedded Microcomputer Systems - Real Time Interfacing, Thomson Asia Pte. Ltd.

• R. H. Barnett, 8051 family of Microcontrollers, PHI.

• Peter Spasov, Microcontroller Technology: The 68HC11, PHI, Fourth Edition

• Dr. Rajkamal, Micro controllers (Architecture, Programming, Interfacing and System Design), Pearson Education.

DIGITAL SIGNAL PROCESSING (MEVD-104)

M.E./ M.Tech. Embeded System and VLSI Design SVITS(INDR)

Micro electronics and VLSI Design SEMESTER-I

DIGITAL SIGNAL PROCESSING SYLLABUS  (MEVD-104)

UNIT I 

Introduction to Discrete Time Signals:Sequences; representation of signals on orthogonal basis; Sampling and Reconstruction of signals.
 
UNIT II 
Discrete Systems:Attributes;Z-Transform;Analysis of LSI systems;Frequency analysis; nverse systems,Discrete Fourier Transform (DFT),Fast Fourier Transform algorithms,Implementation of discrete time systems.
 
UNIT III 
Design of FIR Digital FiltersWindow method, Park-McClellan's method; Effect of finite register length in FIR filter design.
 
UNIT IV 
Design of IIR Digital Filters:Butterworth, Chebyshev and Elliptic Approximations; Lowpass, Bandpass,Bandstop and High pass filters.
 
UNIT V
Introduction to VLSI DSP:Transformations for high speed using pipelining, retiming, parallel processing, and folding techniques;Design of programmable DSPs.

 TEXT / REFERENCE BOOKS

• A.V. Oppenheim and Schafer, Discrete Time Signal Processing, Prentice Hall, 1989.

• John G. Proakis and D.G. Manolakis, Digital Signal Processing: Principle, Algorithms and Applications, Prentice Hall, 1997.

• L.R. Rabiner and B. Gold, Theory and Application of Digital Signal Processing, Prentice Hall, 1992.

• J.R. Johnson, Introduction to Digital Signal Processing, Prentice Hall, 1992.

• D. J. DeFatta, J. G. Lucas and W. S. Hodgkiss, Digital Signal Processing, J Wiley and Sons, Singapore, 1988.

• K.K. Parhi, VLSI Digital Signal Processing Systems: Design and Implementation, Wiley.

ADVANCED LOGIC DESIGN (MEVD-103)

Rajiv Gandhi Technological University, Bhopal (MP)

M.E./ M.Tech. Embeded System and VLSI Design SVITS(INDR)

 ADVANCED LOGIC DESIGN SYLLABUS  (MEVD-103)

UNIT I
Course overview:design concepts,introduction to logic circuit and Verilog.Implementation technology,CMOS logic gates,programmable logic devices.Optimized implementations of logic functions,canonical representations ,Karnaugh maps, factoring,functional decomposition, NAND/NOR networks, bubble pushing.

UNIT II

Verilog data types and operators:modules and ports gate level modeling,time simulation/ scheduler.Circuit issues.Verilog behavioral models,number representation and arithmetic circuits,positional notation,signed numbers,arithmetic operations.
 
UNIT III

Verilog specifications of combinational circuits:combinational logic building blocks, encoders / decoders,arithmetic comparison, etc. The basic latch, gated SR and D latch, master-slave and edge-triggered flip flops, counters, shift registers, Design examples, introduction to finite state machines; introduction to Model Sim.

UNIT IV

Synchronous sequential circuits:design process,state assignment ,hazards, glitches, asynchronous design,Metastability,Noise margins, Power,fan-out,skew Finite state machine design examplesVerilog representations.

TEXT / REFERENCE BOOKS:

• John F. Wakerly, Digital Design, Pearson Education Asia, 3rd Ed.

• M. M. Mano, Digital Design, Pearson Education, 3rd Ed.

• C. H. Roth, Jr., Fundamentals of Logic Design, Jaico Publishing House.

• Fletcher, An Engineering Approach to Digital Design, PHI.

• J. M. Yarbrough, Digital Logic, Thomson Learning.

• Stephen Brown and Zvonko Vranesic, Fundamentals of Digital Logic with Verilog Design, McGraw-Hill Higher Education, 2003, ISBN 0-07-283878-7.

• Samir Palnitkar, Verilog HDL, Prentice Hall, 2nd Edition, 2003, ISBN 0-13-044911-3

CMOS VLSI DESIGN (MEVD-102)

Rajiv Gandhi Technological University, Bhopal (MP)
M.E./ M.Tech. Embeded System and VLSI Design SVITS(INDR)

CMOS VLSI DESIGN SYLLABUS

UNIT-I

VLSI design methodologies:VLSI Design flow, Design Hierarchy, Regularity, Modularity and Locality,VLSI design styles,Design quality,Packaging technology.MOS device design equations , Second order effects, the complementary CMOS Inverter DC characteristics.

UNI-II

Circuit Characterization and Performance Estimation:Parasitic effect in Integrated Circuits ,Resistance estimation,capacitance estimation,Inductance.Switching characteristics,CMOS - Gate transistor sizing,Power dissipation,CMOS Logic Structures,Clocking Strategies.
 
UNITIII

CMOS Process Enhancement & Layout Considerations:Interconnect,circuit elements, Stick diagram, Layout design rules, Latchup, latchup triggering, latchup prevention, Technology related CAD issues.
 
UNIT IV

Subsystem Design: Structured design of combinational logic-parity generator,Multiplexer, code converters.Clocked sequential circuits-two phase clocking,charge storage,dynamic register element,dynamic shift register. Subsystem design process,Design of ALU subsystem, Adders, Multipliers.Commonly used storage/ memory elements.
 
UNIT V

Field Programmable Devices:Definitions of Relevant Terminology,Evolution of Programmable Logic Devices,User-Programmable Switch Technologies,Computer Aided Design (CAD) Flow for FPDs,Programmable Logic,Programmable Logic Structures,Programmable Interconnect, Reprogrammable Gate Array, Commercially Available SPLDs,CPLDs and FPGAs,Gate Array Design,Sea-of-Gates.
 
TEXT / REFERENCE BOOKS:

• D.A. Pucknell, K. Eshraghian, Basic VLSI Design, PHI, 3rd Ed.

• John P. Uyemura, Introduction to VLSI Circuits and Systems, John Wiley & Sons.

• Niel H.E. Weste, K. Eshraghian,, Principles of CMOS VLSI Design, Person, 2nd Ed.

• Mead and L. Conway, Introduction to VLSI Systems, Addison-Wesley.

• A. Mukherjee, Introduction to nMOS and CMOS VLSI systems design, Prentice Hall.

ADVANCED MATHEMATICS (MEVD-101)

Rajiv Gandhi Technological University, Bhopal (MP)
M.E./ M.Tech. Embeded System and VLSI Design SVITS(INDR)
ADVANCED MATHEMATICS MEVD-101 

UNIT I

Solution of Partial Differential Equation (PDE) by separation of variable method, numerical solution of PDE (Laplace, Poisson’s, Parabola) using finite difference methods, Elementary properties of FT, DFT, WFT, Wavelet transform, Haar transform.

UNIT II

Probability, compound probability and discrete random variable. Binomial, Normal, Poisson’s distribution. Sampling distribution, elementary concept of estimation and theory of hypothesis, recurred relations. 

UNIT III

Stochastic process, Markov process transition probability transition probability matrix, just and higher order Markov process, Markov chain. Queuing system, transient and steady state, traffic intensity, distribution queuing system, concepts of queuing models (M/M/1: Infinity/ Infinity/ FC FS), (M/M/1: N/ Infinity/ FC FS), (M/M/S: Infinity/ Infinity/ FC FS)

UNIT IV

Operations of fuzzy sets, fuzzy arithmetic & relations, fuzzy relation equations, fuzzy logics. MATLAB introduction, programming in MATLAB scripts, functions and their application.

UNIT V

Introduction and definition of reliability, derivation of reliability functions, Failure rate, Hazard rate, mean time t future & their relations, concepts of fault tolerant analysis, Elementary idea about decision theory and goal programming.

REFERENCE BOOKS:

• Higher Engineering Mathematics by B.V. Ramana, Tata Mc Hill.

• Advance Engineering Mathematics by Ervin Kreszig, Wiley Easten Edd.

• Applied Numerical Methods with MATLAB by Steven C Chapra, TMH.

• Introductory Methods of Numerical Analysis by S.S. Shastry,

• Introduction of Numerical Analysis by Forberg

• Numerical Solution of Differential Equation by M. K. Jain

• Numerical Mathematical Analysis By James B. Scarborogh

• Fourier Transforms by J. N. Sheddon

• Fuzzy Logic in Engineering by T. J. Ross

• Fuzzy Sets Theory & its Applications by H. J. Zimmersoms

VLSI DESIGN AND EMBEDDED SYSTEM 1ST SEM SYLLABUS

ADVANCED MATHEMATICS (MEVD-101)
 
CMOS VLSI DESIGN (MEVD-102)
 
ADVANCED LOGIC DESIGN (MEVD-103)
 
DIGITAL SIGNAL PROCESSING (MEVD-104)
 
EMBEDDED MICRO-CONTROLLER PROGRAMMING (MEVD-105)
 
LAB -I (MEVD-106)
 
LAB -II (MEVD-107)

VLSI DESIGN AND EMBEDDED SYSTEM SYLLABUS

VLSI DESIGN  I - SEM SYLLABUS 

VLSI DESIGN  II - SEM SYLLABUS 

VLSI DESIGN  III - SEM SYLLABUS

VLSI DESIGN  IV - SEM SYLLABUS